1. Technical Field
The present invention relates to an output buffer circuit in general and, in particular, to an analog output buffer circuit for servo applications. Still more particularly, the present invention relates to an analog output buffer circuit having a high drive capability and a low quiescent power dissipation.
2. Description of the Prior Art
In a disk drive, two different sets of electronic circuits are utilized to read a sequence of four short burst signals originated from a disk surface in order to obtain information as to the location of a read/write head with respect to a track center. A set of four peak-hold circuits is first employed to capture and store the peak amplitude of these four burst signals, with one peak-hold circuit per burst signal. The peak amplitude of each of these burst signals, typically ranging from 0.0 to 1.5 volts, is sustained at an output of their respective peak-hold circuit. A set of four output buffer circuits is then employed to buffer and transfer each individual output voltage signal from the peak-hold circuit to a corresponding load capacitor. Subsequently, a servo system within the disk drive will act upon the voltage signals in the load capacitors for moving the read/write head to the track center, if necessary.
Typically, the peak-hold circuits and the output buffer circuits are incorporated within an integrated circuit (IC) device. Due to their sizes, the load capacitors are generally connected external to the IC device. One requirement for the on-chip output buffer circuits is that they be able to quickly charge and discharge a voltage signal to and from their respective off-chip load capacitor after the voltage signals have been utilized. This allows the on-chip output buffer circuits to be ready to respond to a next set of burst signals.
Referring now to the drawings and in particular to FIG. 1, there is illustrated a schematic diagram of an IC device, in which output buffer circuits are incorporated, along with an off-chip load capacitor. As shown, IC device 30 is connected to a resistor 33 and an off-chip load capacitor 32 in which voltage signals output from IC device 30 are being stored. In addition, resistor 37 and resistor 38 comprise a feedback network around IC device 30. Input V.sub.ref 34 is a reference voltage that establishes the operating current in all of the output buffer circuits within IC device 30. The burst signals are applied to input V.sub.in 36 and subsequently appear at output V.sub.out 39. The voltage waveform of output V.sub.out 39 is similar to that of input V.sub.in 36, except with a voltage gain due to the voltage dividing action provided by resistors 37 and 38. For example, if resistor 37 is 10.0 K.OMEGA. and resistor 38 is 15.0 K.OMEGA., the voltage gain would be approximately 1.67.
During the normal operation of IC device 30, DC power is being continuously consumed by each output buffer circuit in order to maintain a constant output voltage. This DC power consumption must be maintained at quite a high current level (about 2500 .mu.A) in order to allow the output buffer circuit to charge or discharge load capacitor 32 within an acceptable time limit of about 1 .mu.s. However, any time the output voltage is not utilized for charging load capacitor 32, the idle DC power consumption would be considered wasted power. On the contrary, if a lower DC power, such as 300 .mu.A or less, is supplied to the output buffer circuit instead, then the output buffer circuit would take more than 10 .mu.s to charge or discharge the same load capacitor 32. This time penalty will adversely affect the overall performance of the application for which the output buffer circuit is intended.
Consequently, it would be desirable to provide an improved analog output buffer circuit having a high drive capability and yet with a low quiescent power dissipation.